Training Available
Designing with Quartus II
Designing with Nios II & SOPC Builder
Designing with DSP Builder
Schedule
Designing with Quartus II
Description:
This workshop will provide the participant with the fundamental knowledge of developing an FPGA design with Quartus II software. A set of lab exercises will offer opportunities for the participant to familiarise with the FPGA design flow with Quartus II. The individual will be taught how to optimize FPGA resources and improve performances by applying various logic and timing constraints and by analyzing the synthesis, placement and routing results.
Duration: 1 Day
Prerequisite:
- Background knowledge in digital logic designs
- Familiar with at least one design entry method (Schematics/VHDL/Verilog/AHDL)
Skills Developed:
The participant should be able to:
- Create and compile projects
- Set design constraints using the assignment editor
- Analyze clock and input/output timing
- Add timing constraints to achieve better design performance
- Simulate designs using the Quartus II simulator
- Configure and program an Altera device
Schedule
Designing with Nios II & SOPC Builder
Description:
The Nios II workshop will demonstrate the ease of designing an Altera FPGA with a softcore embedded processor. This course is focused on the hands-on hardware and software development using the Nios II Development Kit, Cyclone Edition. The participant will be shown how to integrate a Nios II 32-bit microprocessor and test it in a low cost Cyclone FPGA. This will involve configuring and compiling designs using the Quartus II along with SOPC Builder software tools. The individual will also be using the Nios IDE tools to develop and run the Nios II embedded software. During the workshop, there will be opportunities to participate in discussions about the features and capabilities of Nios II. After this workshop, you should be imbued with the knowledge and confidence in tackling your next system-on-a-programmable-chip (SOPC) design.
Duration: 1 Day
Prerequisite:
- Background knowledge in digital logic designs
- Working knowledge of the Quartus II design software
- Familiar with at least one design entry method (Schematics/VHDL/Verilog/AHDL)
- Fundamental knowledge of programming in C/C++ for embedded systems
Skills Developed:
The participant should be able to:
- Evaluate the Nios II embedded processor and the Nios II Development Kit
- Configure and compile a Nios II embedded processor design using the SOPC Builder tool and
Quartus II software
- Describe the hardware development flow within the Quartus II software, SOPC Builder tool, and
ModelSim-Altera (including how to incorporate custom instructions).
- Understand the software development flow using the new Nios II Integrated Development
Environment (IDE) (including creating, building and debugging embedded software designs,
project-specific headers and library files)
- Know how to access peripherals from the software
Schedule
Designing with DSP Builder
Description:
The DSP builder course will expose the participant with the knowledge of reducing design cycle time with Altera development tools and IP cores. This will involve using the Altera DSP Builder Blockset with Simulink to analyze, design and implement the DSP system. The individual will practice incorporating Altera's intellectual property (IP) cores into the DSP designs by configuring finite impulse response (FIR) filters, numerically controlled oscillators (NCO) and Fast Fourier Transform (FFT) Megacores.
Duration: 1 Day
Prerequisite:
- Background knowledge in digital logic designs
- Fundamental knowledge of DSP design
- Familiar with Altera FPGA architecture
- Working knowledge of the Quartus II design software
- Familiar with at least one design entry method (Schematics/VHDL/Verilog/AHDL)
Skills Developed:
The participant should be able to:
- Investigate features in the Altera FPGA devices (DSP Blocks, Memory Blocks, Logic Elements
(LEs)/Adaptive Logic Modules (ALMs), etc) to achieve higher performances in digital
signal processing systems
- Analyze, design and implement DSP systems using the DSP Builder Blockset with Simulink
- Reduce design cycle time with IP Megacore functions
- Make FPGA resources versus performances tradeoff decisions with the OpenCore Plus evaluation
IP Megacores
- Design and implement digital filters, numerically controlled oscillators, FFT algorithms with Altera FIR,
NCO and FFT Megacores
Schedule
